Eroare de detectare si de manipulare

Error Detection and HandlingEroare de detectare si de manipulare

Introduction to PCI Express Error Management Introducere in Managementul de eroare PCI Express

PCI Express defines a variety of mechanisms used for checking errors, reporting those errors and identifying the appropriate hardware and software elements for handling these errors. PCI Express defineste o varietate de mecanisme utilizate pentru verificarea erorilor, raportarea acestor erori si identificarea hardware corespunzatoare si elemente de software pentru manipularea acestor erori.

PCI Express Error Checking Mechanisms Eroare PCI Express Verificarea Mecanisme

PCI Express error checking focuses on errors associated with the PCI Express interface and the delivery of transactions between the requester and completer functions. Figure 10-1 on page 357 illustrates the scope of the error checking that is the focus of this chapter. PCI Express eroare de verificare se concentreaza pe erorile asociate cu interfata PCI Express si de livrare a tranzactiilor intre solicitant si functiile completer. Figura 10-1 de la pagina 357 ilustreaza sfera de aplicare a verificarii erorilor, care este punctul central al acestui capitol. Errors within a function that do not pertain to a given transaction are not reported through the error handling procedures defined by the PCI Express specification, and it is recommended that such errors be handled using proprietary methods that are reported via device-specific interrupts. Erorile in termen de functie care nu se refera la o anumita operatiune nu sunt raportate de tratare a erorilor prin procedurile stabilite de caietul de sarcini PCI Express, si este recomandat ca astfel de erori sa fie tratate folosind metode brevetate, care sunt raportate prin intermediul specific de intrerupere a dispozitivului. Each layer of the PCI Express interface includes error checking capability as described in the following sections. Fiecare strat de interfata PCI Express include verificarea erorilor de capacitate cum sunt descrise in urmatoarele sectiuni.

Figure 10-1. Figura 10-1. The Scope of PCI Express Error Checking and Reporting Domeniul de aplicare al eroare PCI Express Verificare si raportare

Transaction Layer Errors

The transaction layer checks are performed only by the Requestor and Completer. Stratul de controale tranzactii sunt efectuate numai de catre solicitant si Completer. Packets traversing switches do not perform any transaction layer checks. Pachete de switch-uri care traverseaza, nu efectueaza orice verificari strat de tranzactie. Checks performed at the transaction layer include: Controalele efectuate la stratul de tranzactie includ:

• ECRC check failure (optional check based on end-to-end CRC) ECRC esec verifica (verifica optional pe baza end-to-end CRC)
• Malformed TLP (error in packet format) Malformat TLP (eroare in pachet format)
• Completion Time-outs during split transactions Finalizarea Time-out in timpul tranzactiilor split
• Flow Control Protocol errors (optional) Flow Control erori Protocol (optional)
• Unsupported Requests Neacceptat Cereri
• Data Corruption (reported as a poisoned packet) Coruptia de date (raportata ca un pachet otravit)
• Completer Abort (optional) Completer Abort (optional)
• Unexpected Completion (completion does not match any Request pending completion) Finalizarea neasteptate (finalizarea nu se potriveste nici pana la finalizarea Cerere)
• Receiver Overflow (optional check) Receptor Depasirea (verifica optional)

Data Link Layer Errors Erori de date Link Layer

Link layer error checks occur within a device involved in delivering the transaction between the requester and completer functions. controalelor Link eroari de strat loc in termen de un dispozitiv implicat in realizarea tranzactiei intre solicitantului si functiile completer. This includes the requesting device, intermediate switches, and the completing device. Aceasta include dispozitivul de solicitat, switch-uri intermediare, precum si dispozitivul de completare. Checks performed at the link layer include: Controalele efectuate la nivel de legatura includ:

• LCRC check failure for TLPs LCRC esec verifica pentru TLP
• Sequence Number check for TLP s Numar de ordine pentru a verifica e TLP
• LCRC check failure for DLLPs LCRC esec verifica pentru DLLP
• Replay Time-out Ora Replay-out
• Replay Number Rollover Replay Numarul rollover
• Data Link Layer Protocol errors Data Link Layer protocol erori

Physical Layer Errors Erori strat fizice

Physical layer error checks are also performed by all devices involved in delivering the transaction, including the requesting device, intermediate switches, and the completing device. stratul de controale pentru erori fizice sunt, de asemenea, efectuate de toate dispozitivele implicate in realizarea tranzactiei, inclusiv dispozitivul de solicitat, switch-uri intermediare, precum si dispozitivul de completare. Checks performed at the physical layer include: Controalele efectuate la nivelul stratului fizic includ:

• Receiver errors (optional) receptor erori (optional)
• Training errors (optional) erori de formare (optional)

Error Reporting Mechanisms Eroare mecanismele de raportare

PCI Express provides three mechanisms for establishing the error reporting policy. These mechanisms are controlled and reported through configuration registers mapped into three distinct regions of configuration space. PCI Express prevede trei mecanisme de stabilire pentru politica erorii de raportare. Aceste mecanisme sunt controlate si raportate prin intermediul registrelor de configurare mapate in trei regiuni distincte ale spatiului de configurare. (See Figure 10-2 on page 360.) The various error reporting features are enabled as follows: (A se vedea Figura 10-2 de la pagina 360 ca.) raportarea erorilor caracteristicii sunt activate si urmeaza:

• PCI-compatible Registers (required) - this error reporting mechanism provides backward compatibility with existing PCI compatible software and is enabled via the PCI configuration Command Register. -Compatibil Registru PCI (obligatoriu) - aceasta eroare a mecanismului de raportare ofera compatibilitate cu software-ul compatibil PCI existent si este activat prin intermediul de configurare PCI Comandamentul registru. This approach requires that PCI Express errors be mapped to PCI compatible error registers. Aceasta abordare presupune ca PCI Express erorea poate fi mapata la registrele de eroare compatibile PCI.
• PCI Express Capability Registers (required) - this mechanism is available only to software that has knowledge of PCI Express. PCI Express Capacitate Registre (obligatoriu) - acest mecanism este disponibil numai pentru software-ul care are cunostinte din PCI Express. This required error reporting is enabled via the PCI Express Device Control Register mapped within PCI-compatible configuration space. Aceasta eroare de raportare ceruta este activata prin intermediul dispozitivelor PCI Express de control Registrul mapat in spatiul de configurare compatibil-PCI.
• PCI Express Advanced Error Reporting Registers (optional) - this mechanism involves registers mapped into the extended configuration address space. PCI Express avansata Error Reporting Registre (optional) - Acest mecanism implica registrele mapate in configuratia spatiului de adrese extinse. PCI Express compatible software enables error reporting for individual errors via the Error Mask Register. PCI Express permite un software compatibil activeaza eroarea de raportare pentru erori individuale, prin intermediul masca de eroare registru.

Figure 10-2. Figura 10-2. Location of PCI Express Error-Related Configuration Registers Locatia de eroare de configurare PCI-Express Registre

The specification refers to baseline (required) error reporting capabilities and advanced (optional) error reporting capabilities. Caietul de sarcini se refera la valoarea initiala (a cere) si capabilitati avansate de raportare a erorilor (optional) de raportare capabilitati de eroare. The baseline error reporting mechanisms require access to the PCI-compatible registers and PCI Express Capability registers (bullets 1 and 2 above), while advanced error reporting (bullet 3) requires access to the Advanced Error Reporting registers that are mapped into extended configuration address space as illustrated in Figure 10-2 . Eroarea de baza, mecanismele de raportare necesita acces la registrele compatibile PCI si capacitatea de PCI Express registrele (gloante 1 si 2 de mai sus), in timp ce eroarea de raportare avansata (glont 3) necesita acces la registrele avansate de eroare de raportare care sunt mapate in spatiul de configurare adresa prelungita cum este ilustrata in figura 10-2 . This chapter details all error reporting mechanisms. In acest capitol gasim toate detaliile de eroare ale mecanismele de raportare.

Error Handling Mechanisms Eroare de mecanismele de tratare

Errors are categorized into three classes that specify the severity of an error as listed below. Note also the specification defines the entity that should handle the error based on its severity: Erorile sunt clasificate in trei clase care specifica severitatea unei erori ce este afisata mai jos. Retineti, de asemenea, caietul de sarcini defineste entitatea care ar trebui sa se ocupe de eroare bazata pe severitatea acesteia:

• Correctable errors - handled by hardware erori corectabile - manipulate de hardware
• Uncorrectable errors-nonfatal - handled by device-specific software eroei necorectabile erori nefatale - manevrate de-software specifice dispozitiv
• Uncorrectable errors-fatal - handled by system software necorectabile erori nefatale - manipulate de software de sistem

By defining errors into these classes, error handling software can be partitioned into separate handlers to perform the actions required for a given platform. Prin definirea de erori in aceste clase, software-ul de eroare de manipulare poate fi divizat in cele care opereaza separate, pentru a efectua actiunile necesare pentru o platforma de dat. The actions taken based on severity of an error might range from monitoring the effects of correctable errors on system performance to simply resetting the system or PCI Express sub-system in the event of a fatal error. Masurile luate in functie de severitatea unei erori pot varia de la monitorizarea efectelor de erori corectabile asupra performantei sistemului de resetare a sistemului sau pur si simplu PCI Express sub-sistemul in caz de o eroare fatala.

Note that regardless of the severity of a given error, software can establish a policy whereby any error can be reported to the system (via the Root Complex) for the purpose of tracking and logging. Retineti ca, indiferent de gravitatea unei erori de date, software-ul poate sa stabileasca o politica prin care orice eroare poate fi raportata la sistem (prin intermediul Complexul Root), in scopul de urmarire si sa va autentificati. (See page 390 for details.) (Vezi pagina 390 pentru detalii.)

[ Team LiB ] Echipa [Lib]

[ Team LiB ] Echipa [Lib]

Sources of PCI Express Errors Surse de erori PCI Express

This section provides a more detailed description of the error checks made by PCI Express interfaces when handling transactions. Aceasta sectiune ofera o descriere mai detaliata a verificarilor erori facute de interfete PCI Express atunci cand tranzactiile de manipulare.

ECRC Generation and Checking ECRC generatie si Verificarea

ECRC generation and checking is optional and only supported by devices and systems that implement Advanced Error Reporting. generatie ECRC si verificarea este optional si este sustinuta numai de dispozitive si sisteme care punerea in aplicare a avansat de raportare erori. Devices that support ECRC must implement the Advanced Error Capabilities and Control Register. Dispozitive care accepta ECRC trebuie sa puna in aplicare avansata eroare Capabilitatile si control registru. Configuration software checks this register to determine if ECRC is supported, and to enable ECRC support. De configurare de software controale acest registru pentru a determina daca ECRC este sustinuta, si pentru a permite ECRC sprijin.

A PCI Express device that originates a transaction (Request or Completion) can create and append a 32-bit CRC (within the digest field) that covers the header and data portions of the transaction. Un dispozitiv PCI Express care provine o tranzactie (cerere sau completare) poate crea si anexati o bit CRC-32 (in cadrul digera domeniu) care acopera antet si portiuni de date ale tranzactiei. This CRC is termed end-to-end (ECRC) and is typically checked and reported by the ultimate recipient of the transaction. Acest CRC este numit end-to-end (ECRC) si este de obicei verificate si raportate de catre destinatarul final al tranzactiei. Switches in the path between the originating and receiving devices may optionally check and report ECRC errors, or merely forward the packet without checking the ECRC. Intreruperi in calea intre efectuarea si primirea dispozitivele pot verifica optional si raporteaza erori ECRC, sau doar inainte de pachete fara a verifica ECRC. If a Switch detects an ECRC error it must still forward the packet unaltered as it would any other packet. In cazul in care un Switch detecteaza o eroare ECRC trebuie inca inainte de pachete de nealterat, deoarece ar orice alt pachet. Switches may also be the originator or recipient of a transaction in which case they can participate in ECRC generation and checking in this role. Comutatoare pot fi, de asemenea, initiator sau de beneficiar al unei tranzactii, caz in care acestea pot participa la ECRC generatie si de verificare in acest rol.

The actions taken when an ECRC error is detected is considered beyond the scope of the specification. However, the possible actions taken will likely depend on whether the ECRC error occurs in a Request or Completion: Masurile luate atunci cand o eroare este detectat ECRC este considerat dincolo de sfera de aplicare a caietului de sarcini. Cu toate acestea, actiunile posibile luate vor depinde probabil daca eroarea ECRC apare intr-o cerere sau de completare:

• ECRC in Request - completers that detect an ECRC error may simply drop the transaction without forwarding it to the receiving function and as a result not return a completion. ECRC in cerere - completers care detecteaza o eroare ECRC ar putea sa scada, pur si simplu tranzactia fara transmiterea la functia de primire si ca urmare nu returneze o finalizare. This ultimately will result in a completion time-out within the requesting device. Acest lucru va duce in cele din urma intr-un timp finalizarea-out in interiorul dispozitivului, solicitante. The requester could then reschedule the transaction under software control. Solicitantul ar putea reprograma apoi tranzactia sub control software.
• ECRC in Completion - requesters that detect an ECRC error may drop the packet and report the error to the function's device driver via a function-specific interrupt. The driver would check the status bits in the Uncorrectable Error Status Register to detect the nature of the error and potentially reschedule the transaction in the event that a prefetchable address location was being accessed. ECRC in completare - solicitantii care detecteaza o eroare ECRC ar putea sa scada sub forma de pachete si raportul de eroare pentru a driver de dispozitiv functie printr-o functie specifica de intrerupere. Sofer ar verifica bitii de stare in eroare Uncorrectable registrul STATUS pentru a detecta natura erorii potential si sa reesaloneze o tranzactie in cazul in care o locatie adresa prefetchable a fost accesat.

Note that ECRC errors may also result in error messages being sent to the host for handling or logging. Retineti ca erorile ECRC poate avea ca rezultat, de asemenea, mesaje de eroare a fi trimis la gazda pentru manipularea sau de logare.

Data Poisoning (Optional) Datele de otravire (optional)

Data poisoning provides a way of indicating that data associated with a transaction is corrupted. otravire Data ofera o modalitate de a indica ca datele asociate cu o tranzactie, este corupt. When a TLP is received that contains a data field, the recipient will know that data is corrupted if the poisoned bit is set. Figure 10-3 illustrates the Error/Poisoned bit (EP) located within the first Dword of a packet. Atunci cand un TLP este primit care contine un camp de date, destinatarul va sti ca de date este corupt, daca biti otravit este setat. Figura 10-3 ilustreaza eroare / bit Otravit (PE) situate in DWORD prima un pachet.

Figure 10-3. Figura 10-3. The Error/Poisoned Bit within Packet Headers Eroare / bit Otravit in headerul pachetului

The specification includes three examples of data corruption that could result in data poisoning being used. Caietul de sarcini cuprinde trei exemple de date de coruptie care ar putea duce la otravirea date fiind utilizate. In each of these cases, the error can be forwarded to the recipient via the data poisoning bit in the transaction header. In fiecare dintre aceste cazuri, eroarea poate fi transmis destinatarului prin otravire biti de date in antetul de tranzactie.

• When a Requester wishes to perform a Memory Write transaction it must first fetch the data it wishes to send to the completer from local memory. Atunci cand un solicitant doreste sa efectueze o tranzactie de memorie Scrie trebuie sa descarcati mai intai datele pe care le doreste sa trimita la completer din memorie locale. In the event of a parity error when reading the data, the data can be marked as poisoned. In cazul unei erori de paritate atunci cand citirea datelor, acestea pot fi marcate ca otravit.
• When a Completer must return data in response to a Memory Read request, the data it fetches from memory may incur a parity error. Atunci cand un Completer trebuie sa se intoarca de date ca raspuns la o cerere Cititi Memorie, datele pe care le preia din memorie poate suporta o eroare de paritate.
• Data that is stored in a cache or buffer that has error checking may also result in data corruption being detected. Datele care sunt stocate intr-un cache sau tampon care are verificarea erorilor poate duce, de asemenea, in coruptie date fiind detectate. The specification does not indicate where these caches or buffers may be located, but it is conceivable that any device that originates a transaction or forwards it may indicate that the data has been poisoned. Caietul de sarcini nu indica in cazul in care aceste cache sau tampoane pot fi situate, dar nu este exclus ca orice dispozitiv care provine o tranzactie sau inainte se poate indica faptul ca datele au fost otravit.

The specification states that data poisoning applies to data associated with both posted and non-posted writes and read completions. Caietului de sarcini care prevede otravire a datelor se aplica datelor asociate cu atat postat si non-postat scrie si citi completarile. Therefore data poisoning can be used in conjunction with Memory, I/O, and Configuration transactions that have a data payload. Prin urmare, datele de otravire pot fi folosite in conjunctie cu memorie, I / O, si tranzactii de configurare, care au o sarcina utila de date.

Data poisoning can only be done at the transaction layer of a device. Datele otravire poate fi realizat numai la nivelul stratului de tranzactie a unui dispozitiv. The link layer does not process or in any way affect the contents of the TLP header. Stratul de link-ul nu procesul sau afecteaza in niciun fel continutul antetul TLP. The transaction layer indicates that data is corrupted by setting the Data Error/Poisoned bit (E/P) in the Write request or Read Completion transaction header. Stratul de tranzactie date indica faptul ca este corupt prin stabilirea de date de eroare / bit Otravit (E / P) in cererea Scrie sau tranzactie Citeste antet completare.

Data poisoning errors are enabled and reported via the Uncorrectable Error Registers. Datele erori otravirii sunt activate si raportate prin intermediul Uncorrectable registrele de eroare.

TC to VC Mapping Errors TC la erori de cartografiere CV

All PCI Express ports that implement the extended VC capability (endpoints, switches, and root ports) must check to verify that the TC of each inbound packet is mapped to an active VC. Toate porturi PCI Express ca punerea in aplicare a extins capacitatea de CV (obiective, switch-uri, precum si porturile de root) trebuie sa verifice pentru a verifica daca TC de fiecare pachet intrare este mapata la o activa CV. Packets with TC's that fail this check are treated as malformed TLPs. Pachete cu TC ca acest control nu sunt tratate ca TLPs malformate. Similarly, when switches forward packets, they must also verify that the target outbound port of the switch also supports the packet's TC. In mod similar, atunci cand transmite pachetele de switch-uri, acestea trebuie sa verifice, de asemenea, ca obiectivul de portul de iesire a comutatorului sprijina, de asemenea pachetului TC. If not, the packet is treated as a malformed TLP. Daca nu, sub forma de pachete este tratata ca o malformat TLP.

A requester or completer may implement more than one Virtual Channel (VC) and enable more than one Traffic Class (TC). Un solicitant sau completer poate pune in aplicare mai mult de un canal virtual (CV) si pentru a permite mai mult de o clasa de trafic (TC). If the device core issues a request to send a transaction with a TC number that is not enabled (pointing to an active VC) within the TC to VC mapping tables, the transaction is rejected and a malformed TLP is indicated. In cazul in care problemele de baza aparatul o cerere pentru a trimite o tranzactie cu un numar de TC, care nu este activat (indica spre un activ CV) in cadrul TC la tabele de cartografiere CV, tranzactia este respins si un malformat TLP este indicat. If the device has implemented the PCI Express Virtual Channel Capability structure (supports multiple VCs and/or TC filtering), then the malformed TLP error is detected at the transmitting device. However, if the device only supports the default TC0/VC0 configuration, then this error would be detected at the first receiving device along the packet's path that implements the extended VC capability and applies TC filtering. In cazul in care aparatul a pus in aplicare PCI Express Virtual Channel structura Capacitate (accepta VCs multiple si / sau TC de filtrare), apoi malformat TLP eroare este detectat la aparatul de emisie Totusi, daca aparatul accepta numai configuratia TC0/VC0 implicit, apoi aceasta eroare ar putea fi detectat de la primirea primul dispozitiv de-a lungul pachetului calea care pune in aplicare extins capacitatea de CV si se aplica TC filtrare.

Note also that the TC to VC mapping is a transaction layer function. Retineti, de asemenea, ca TC de cartografiere CV este o functie tranzactie strat. (See ' Assigning TCs to each VC - TC/VC Mapping ' on page 262 for details). (A se vedea ' Atribuirea TCS pentru fiecare CV - CT / CV de cartografiere 'de la pagina 262 pentru detalii).

Link Flow Control-Related Errors Link Erori de control legate de debit

Prior to forwarding the packet to the link layer for transmission across the link, the transaction layer must check flow control credits to ensure that the receive buffers in the adjacent node (switch or completer) have sufficient room to hold the transaction. Inainte de transmiterea de pachete de la stratul de link-ul pentru transmiterea peste link-ul, stratul de tranzactie trebuie sa verifice de control al fluxului de credite sa se asigure ca primesc tampoane in nod adiacente (comutator sau completer) au spatiu suficient sa detina tranzactie. Flow control protocol errors may occur that will likely prevent transactions from being sent. Fluxul de erori protocolul de control poate sa apara ca va preveni probabil tranzactiile de a fi trimis. These errors can be reported to the Root Complex and are considered uncorrectable. Aceste erori pot fi raportate la Complexul Root si sunt considerate uncorrectable. The uncorrectable error registers are used to enable and check status for Flow Control (FC) errors. Eroare uncorrectable registre sunt utilizate pentru a permite si a verifica starea de Flow Control (FC) erori. The specification does not require that these errors be checked and reported. Caietul de sarcini nu impune ca aceste erori sa fie verificate si raportate.

All five conditions that cause flow control related errors (flow control protocol errors and receiver overflow errors) are detected by and associated with the port receiving the flow control information. Toate cele cinci conditii care cauzeaza erori de control al fluxului (protocolul de control al fluxului de erori si erori preaplin receptor) sunt detectate de si asociate cu portul care primeste informatiile de control al fluxului. These error conditions are: Aceste conditii de eroare sunt:

• The specification defines the minimum credit size that can be initially reported for each Flow Control type. Caietul de sarcini defineste dimensiunea minima de credit care poate fi initial raportate pentru fiecare tip de control al debitului. During FC initialization for any Virtual Channel, if a receiver fails to advertise VC credit value equal to or greater than those permitted, it is considered an FC protocol error. In timpul Initializarea FC pentru orice Virtual Channel, in cazul in care un receptor nu pentru a face publicitate CV valoarea creditului egala sau mai mare decat cele permise, aceasta este considerata o eroare de protocol FC.
• The maximum number of data payload credits that can be reported is restricted to 2048 unused credits and 128 unused credits for headers. Numarul maxim de date sarcina utila de credite care pot fi raportate este limitata la 2048 de credite neutilizate si 128 de credite neutilizate pentru anteturi. Exceeding these limits is considered an FC protocol error. Care depasesc aceste limite este considerata o eroare de protocol FC.
• During FC initialization receivers are allowed to report infinite FC credits. Receptoare in timpul Initializarea FC se permite sa raporteze FC credite infinit. FC updates are required following initialization. FC actualizari sunt necesare urmatoarele initializare. FC updates are allowed providing that the credit value field is set to zero, which is ignored by the recipient. FC actualizari sunt permise cu conditia ca domeniu de credit valoare este setata la zero, ceea ce este ignorat de catre destinatar. If the data field contains any value other than zero, it is considered an FC protocol error. In cazul in care campul de date contine orice alta valoare decat zero, aceasta este considerata o eroare de protocol FC.
• During FC initialization either the Data or header FC advertisement (but not both) for a given FC type may be infinite. In timpul de initializare FC fie date sau antetul FC publicitate (dar nu ambele) pentru un anumit tip de FC poate fi infinita. FC update packets are required to report credits for the buffer that advertised limited FC credits. FC pachetele de actualizare sunt obligate sa raporteze credite pentru tampon, care publicitate limitat creditele FC. However the update credit value for the buffer advertised as infinite must be set to zero and ignored by the receiver. Cu toate acestea, valoarea creditului update pentru tampon publicitati infinit trebuie sa fie setat la zero si ignorate de catre receptor. A non-zero credit value could cause an FC protocol error. O-zero, valoarea creditului nu ar putea cauza o eroare de protocol FC.
• A specific check can be made at the receiving port to determine if a flow control receive buffer has overflowed, resulting in lost data. Un control specifice pot fi efectuate in portul primeste pentru a determina daca un control al fluxului primi tampon a umplut, ducand la pierderea datelor. This check is optional and considered an FC protocol error. Aceasta verificare este optional si a considerat-o eroare de protocol FC.

Flow Control Protocol errors are reported as uncorrectable errors, if supported and enabled. Flow Control erori protocol sunt raportate ca erori uncorrectable, daca este acceptata si a permis.

Malformed Transaction Layer Packet (TLP) Malformat pachete Transaction Layer (TLP)

When the ultimate recipient of a transaction receives a request or completion packet into the transaction layer, the packet format is checked for violations of the TLP formatting rules. In cazul in care destinatarul final al unei tranzactii primeste o cerere sau realizarea de pachete in stratul de tranzactie, formatul de pachete este verificat pentru incalcari ale normelor de formatare TLP. The specification defines the following items that cause a malformed packet: Caietul de sarcini defineste urmatoarele elemente care determina un pachet malformat:

• Data payload exceeds Max payload size. sarcina utila de date depaseste sarcina utila dimensiunea max.
• The actual data length does not match data length specified in the header. Lungimea datele reale nu se potriveste cu lungimea de date specificate in antet.
• Start Memory DW address and length field results in the transaction crossing a 4KB boundary. Start Memorie adresa DW si rezultatele domeniul lungimea in tranzactie care traverseaza o frontiera 4KB.
• TD field =1 (indicating Digest included) but no digest field is present. domeniul TD = 1 (indicand Digest inclus), dar digera nici un camp este prezent.
• Byte Enable violation detected. Octet incalcare Activeaza detectate.
• Packets which use an undefined Type field values. Pachete care utilizeaza un tip de camp valori nedefinite.
• Multiple completion packets are used to send read data back to the requester and the data size returned in any of the completion packets violates the Read Completion Boundary (RCB) value. Mai multe pachete de finalizare sunt folosite pentru a trimite inapoi la citeasca datele solicitantului si datele dimensiunea intors in oricare din pachetele finalizarea incalca Citeste Finalizarea limita (BCR), valoarea.
• Completions with a Configuration Request Retry Status in response to a Request other than a Configuration Request. Completari cu o cerere de configurare Reincercati Status ca raspuns la o alta cerere decat o Cerere de configurare.
• Traffic Class field (TC) contains a value not assigned to an enabled Virtual Channel (VC) within the TC - VC mapping for the receiving device. Clasa domeniul traficului (TC) contine o valoare care nu atribuite unui activat Virtual Channel (CV) in cadrul TC - CV de cartografiere pentru a dispozitivului de primire.
• Transaction type requiring use of TC0 has TC value other than zero: Tipul care necesita utilizarea de tranzactie a TC0 TC are o valoare, altele decat zero:
• I/O Read or Write requests and completions I / O Read sau a cererilor Scrie si completarile
• Configuration Read or Write requests and completions Citeste sau a cererilor de configurare Scrie si completarile
• Error messages Mesajelor de eroare
• INTx messages INTx mesaje
• Power Management messages Power Management mesaje
• Unlock messages Deblocare mesaje
• Slot Power messages Slot de alimentare mesaje
• Routing is incorrect for transaction type (eg, transactions requiring routing to Root Complex detected moving away from Root Complex). Rutare este incorecta pentru tipul de tranzactie (de exemplu, tranzactii care necesita dirijare a Root Complexul detectat trecerea de la Complexul Root).

Split Transaction Errors Split Transaction Erori

A variety of failures can occur during a split transaction. O varietate de erori pot aparea in timpul unei tranzactii despicate. When a transaction request is sent to a destination device a completion transaction is expected in response (except for Memory Write and Message transactions which are posted transactions). The various failure modes that can occur are discussed in the following sections. Atunci cand o cerere de tranzactie este trimis la un dispozitiv de destinatie o tranzactie finalizare este de asteptat ca raspuns (cu exceptia de Memorie Scrie si tranzactiile mesaj care sunt postate tranzactii). Esec diferitele moduri care pot aparea sunt discutate in sectiunile urmatoare.

Unsupported Request Cerere de neacceptat

When a recipient of a transaction request detects that it does not support this transaction, it returns a completion transaction with unsupported request (UR) specified in the completion status field. Atunci cand un beneficiar al unei cereri tranzactie detecteaza ca acesta nu are suport pentru aceasta tranzactie, returneaza o tranzactie finalizarea cu cererea neacceptata (UR) specificate in domeniul starii de finalizare. The specification defines a number of specific conditions that cause UR to be returned in the completion status field: Caietul de sarcini defineste un numar de conditii specifice care produc UR sa fie returnate in domeniul statutul finalizare:

• Request type not supported. Cerere tip nu sunt acceptate.
• Message request received with unsupported or undefined message code. cerere mesaj primit mesaj cu codul nedefinite sau neacceptat.
• Request does not reference address space mapped within device. Cererea nu spatiu de referinta adresa mapate in dispozitiv.
• Request contains an address that cannot be routed to any egress port of a bridge or a switch (ie, address is not mapped to any port's base and limit registers). Cererea contine o adresa care nu pot fi dirijate catre orice port iesirea dintr-un pod sau un switch (adica, adresa nu este mapata la portul de baza si orice limita de registre).
• Poisoned Write Request addresses an I/O or Memory mapped control space in the Completer. Otravit Scrie Cerere abordeaza o I / O sau memorie mapate in spatiul de control Completer. Such transactions must be discarded by the Completer and reported as a UR. Astfel de tranzactii trebuie sa fie eliminate prin Completer si raportate ca o UR.
• PCI Express endpoint device receives a MRdLk (lock) transaction. Obiectivul dispozitiv PCI Express primeste o MRdLk (blocare) tranzactia. (Recall that lock is not supported by endpoint devices.) (Sa nu uitam ca de blocare nu este sustinuta de dispozitive terminale.)
• The downstream port of the Root Complex or Switch receives a configuration request with a Device number of 1-31. In aval de portul Complexul radacina sau Switch primeste o cerere de configurare cu un numar de dispozitive de 1-31. The port must terminate the transaction and not initiate a configuration transaction on the downstream link. Port trebuie sa termina tranzactia si nu initia o tranzactie de configurare pe link-ul din aval. Instead a completion transaction is returned with UR status. In schimb, o tranzactie finalizare este returnat cu statutul UR.
• A configuration access that targets an un-implemented Bus, Dev, or Function results in termination of the transaction, and a completion transaction is returned with UR status. Un acces de configurare care vizeaza o implementat de autocar ONU, Dev, sau functia duce la incetarea operatiunii, precum si o tranzactie finalizare este returnat cu statutul UR.
• Type 1 configuration request received at endpoint. De tip 1, cererea de configurare primit la final.
• A completion is received at the requester with a reserved completion code. O finalizare este primit la solicitantul cu un cod de finalizare rezervate. This must be interpreted as a UR. Aceasta trebuie sa fie interpretata ca o UR.
• A function is in the D1 or D2 power management states and a request other than a configuration request is received. O functie este in state sau D2 de gestionare a puterii D1 si o cerere, altele decat o cerere de configurare este primit.
• A configuration access that targets a bus that is not in the range of buses downstream of that port according to the secondary and subordinate register values. Un acces de configurare ca obiectivele pe un autobuz care nu este in gama de autobuze in aval de portul respectiv, in conformitate cu valorile si subordonate registru secundar.
• A configuration request passing through a PCI Express - PCI Bridge for which the Extended Register Address field is non-zero that is directed toward a PCI bus that does not support Extended Configuration Space. O cerere de configurare trece printr-un PCI Express - PCI Bridge pentru care extinderea Adresa domeniul Registrul este non-zero, care este orientata spre o magistrala PCI care nu are suport pentru extinderea Configurare Space.
• A transaction headed for a port with the Reject Snoop Transactions field set in the VC Resource Capability register that does not have the No Snoop bit set in the TLP header. O tranzactie condus de un port cu Snoop Respingere domeniul Tranzactii stabilite in Resurse CV inregistra capabilitatea care nu are pic Snoop nr stabilite in antetul TLP.
• A transaction is targeting a device on a PCI bus but is Master Aborted after the request was accepted by the bridge. O operatiune este un dispozitiv de orientare pe o magistrala PCI, dar este Maestru terminata dupa care cererea a fost acceptata de catre pod.

Completer Abort Completer Abort

These type of error checks are optional. Aceste tipuri de controale de eroare sunt optionale. Three circumstances can occur that could result in a Completer returning an abort to the Requester: Trei imprejurari pot aparea care ar putea rezulta intr-o Completer trimiterea unui abandona la solicitantului:

1. A Completer receives a request that it cannot complete because the request violates the programming rules for the device. Un Completer primeste o cerere ca nu poate termina, deoarece cererea incalca normele de programare pentru dispozitiv. As an example, some devices may be designed to permit access to a single location within a specific DWord, while any attempt to access the other locations within the same DWord would fail. Such restrictions are not violations of the specification, but rather legal restrictions associated with an implementation-specific programming interface for this function. Ca un exemplu, unele dispozitive pot fi proiectate pentru a permite accesul la o singura locatie, intr-un anumit DWord, in timp ce orice incercare de a accesa alte locatii in acelasi DWord ar esua. Astfel de restrictii nu sunt incalcari ale caietului de sarcini, ci mai degraba restrictiile legale asociate cu o interfata de programare specifice de implementare pentru aceasta functie. Accesses to such devices are based upon the expectation that only the device-driver for this device understands how to access its function. Accese de astfel de dispozitive se bazeaza pe presupunerea ca numai dispozitiv driverul pentru acest dispozitiv intelege modul de acces la functia sa.
2. A completer receives a request that it cannot process because of some permanent error condition associated with the device. Un completer primeste o cerere care nu poate procesa din cauza unor permanenta stare de eroare asociat cu aparatul. For example, a PCI Express wireless LAN card that is not accepting PCI Express transactions because it will not transmit or receive data over its radio unless there is an approved antenna attached. De exemplu, un PCI Express card de LAN fara fir care nu accepta tranzactii PCI Express, din cauza ca nu va transmite sau primi date prin radio sa, daca nu este o antena aprobat atasat.
3. A PCI Express to PCI Bridge may receive a request that targets a PCI or PCI-X bus. O PCI Express PCI Bridge pot primi o cerere care vizeaza un PCI sau PCI-X. These buses support a signaling convention that allows the target device to indicate that it has aborted the request (target abort) because it cannot complete the request due to some permanent condition or violation of the function's programming rules. Aceste autobuze sprijini o conventie de semnalizare care permite dispozitivului tinta pentru a indica faptul ca a avortat cererea (abandona tinta), deoarece nu poate finaliza cererea din cauza unor conditii permanenta sau incalcare a normelor de functia lui de programare. The bridge in turn would return a PCI Express completion transaction indicating CA status. Pod la randul sau, ar reveni un PCI Express finalizarea tranzactiei, indicand starea CA.

A Completer that aborts a request may report the error to the Root Complex as a Non-Fatal Error message. Further, if the aborted request requires a completion, the completion status would be reported as CA. Un Completer ca aborts o cerere poate raporta eroarea la Complexul Root ca-Fatal Error mesaj non Suplimentare in cazul in care cererea avortat necesita o finalizare, statutul de finalizare ar fi raportat ca CA.

Unexpected Completion Finalizarea neasteptate

A completion transaction that arrives at a Requester uses the transaction descriptor (Requester ID and Tag) to match the request to which this completion applies. O tranzactie finalizarea care ajunge la un solicitant foloseste descriptor tranzactiei (ID-ul solicitantului si Tag) pentru a se potrivi cererea la care se aplica acest finalizare. In rare circumstances the transaction descriptor may not match a request that is pending completion. In cazuri rare descriptor tranzactia nu se potriveasca cu o cerere care este in asteptarea finalizarii. The typical reason for this unexpected completion is that the completion was mis-routed on its journey back to the intended requester. Motivul tipic pentru acest finalizare neasteptata este faptul ca finalizarea a fost mis-rutate pe drumul inapoi la solicitantului destinate. Consequently, two requesters will be surprised: In consecinta, doua solicitantii vor fi surprins:

1. the requester that has received the unexpected completion, and solicitantul care a primit finalizarea neasteptate, si
2. the requester that fails to receive the completion (thereby causing a completion time-out) solicitantului care nu reuseste sa primeasca finalizarea (determinand astfel o finalizarea time-out)

A Non-Fatal Error message can be sent by the device that receives the unexpected completion. Un non-letale Mesaj de eroare pot fi trimise prin dispozitiv care primeste finalizarea neasteptate.

Completion Time-out Timp de completare-out

The previous discussion points out that a completion transaction can be routed to the wrong device. Discutia anterioara subliniaza ca incheierea unei tranzactii pot fi dirijate la aparat gresit. Consequently, the pending request will never receive its completion. In consecinta, cererea in asteptarea nu va primi niciodata finalizarea acestuia. The specification defines the completion time-out mechanism to identify this situation and report the error to requester software for possible recovery. Caietul de sarcini defineste time-out mecanism de finalizare pentru a identifica aceasta situatie si prezinta un raport de eroare pentru a solicitantului de software pentru recuperare posibil. The specification clearly defines that the intent of the completion time-out is to detect when a completion has no reasonable chance of returning and not related to expected latencies associated with split transactions. Caietul de sarcini defineste clar ca intentia timp finalizare-out este de a detecta momentul in care o finalizare are nici o sansa rezonabila de a se intoarce si nu au legatura cu latenta de asteptat asociate tranzactiilor despicate.

The completion time-out mechanism must be implemented by any device that initiates requests that require completions to be returned. Finalizarea-mecanismul de timp trebuie sa fie puse in aplicare de catre orice dispozitiv care initiaza cererile care necesita completari care urmeaza sa fie returnate. An exception is allowed for devices that only initiate configuration transactions. O exceptie este permisa pentru dispozitivele care initiaza numai tranzactiilor de configurare. The specification defines the permissible range of the time-out value as follows: Caietul de sarcini defineste gama admisa a-out valoarea timp, dupa cum urmeaza:

• It is strongly recommended that a device not time-out earlier than 10ms after sending a request; however, if the device requires greater granularity a time-out can occur as early as 50µs. Este recomandat ca un dispozitiv nu time-out mai devreme de 10 ms, dupa care trimite o cerere; cu toate acestea, daca dispozitivul necesita o mai mare granularitate un interval de timp pot sa apara cat mai devreme 50μs.
• Devices must time-out no later than 50ms. Dispozitivele trebuie sa time-out nu mai tarziu de 50ms.

Note that for Memory Read requests a request may require two or more completions to return all of the requested data. Retineti ca pentru cererile de memorie Citeste o cerere pot solicita doua sau mai multe completari pentru a reveni toate datele solicitate. All of the data must be returned prior to the time-out. Toate datele trebuie sa fie returnate inainte de time-out. If some but not all of the data has been returned when the time-out occurs, the requester may either discarded or keep the data. Daca unii, dar nu toate datele a fost returnat in cazul in care apare time-out, solicitantul poate sa fie eliminat sau sa pastrati date.

Error Classifications Eroare Clasificari

Errors are categorized into three classes that specify the severity of an error as listed below. Note also the specification defines the entity that should handle the error based on its severity: Erorile sunt clasificate in trei clase care specifica severitatea o eroare enumerate mai jos. Retineti, de asemenea, caietul de sarcini defineste entitatea care ar trebui sa se ocupe de eroare bazate pe severitatea acesteia:

• Correctable errors - handled by hardware erori corectabile - manipulate de hardware
• Uncorrectable errors-nonfatal - handled by device-specific software Uncorrectable erori-nonfatal - manevrate de-software specifice dispozitiv
• Uncorrectable errors-fatal - handled by system software Uncorrectable erori-fatale - manipulate de software de sistem

By defining errors into these classes, error handling software can be partitioned into separate handlers to perform the actions required of a given platform. Prin definirea erori in aceste clase, software-ul de eroare de manipulare poate fi divizata in care opereaza separate, pentru a efectua actiunile necesare unei platforme de dat. The actions taken based on severity of an error might range from monitoring the effects of correctable errors on system performance to simply resetting the system in the event of a fatal error. Masurile luate in functie de severitate a unei erori pot varia de la monitorizarea efectelor de erori corectabile asupra performantei sistemului de resetare a sistemului pur si simplu in caz de o eroare fatala.

Note that regardless of the severity of a given error, software can establish a policy whereby the system is notified of all errors for the purpose of tracking and logging each category. Retineti ca, indiferent de gravitatea unei erori de date, software-ul poate sa stabileasca o politica prin care sistemul este notificat de toate erorile, in scopul de urmarire si exploatare forestiera fiecare categorie.

Correctable Errors Corectabile Erori

The specification defines correctable errors as those errors that are corrected solely by hardware. Caietul de sarcini defineste erori corectabile ca aceste erori care sunt corectate doar de hardware. Such errors may have an impact on performance (ie, latency and bandwidth), but no information is lost as a result of the error. These types of error can be reported to software, which can take a variety of actions, Including: Astfel de erori pot avea un impact asupra performantei (de exemplu, latenta si latimea de banda), dar nu exista informatii pierdut ca urmare a erorii. Aceste tipuri de erori pot fi raportate la software-ul, care poate lua o varietate de actiuni, inclusiv:

• log the error jurnal de eroare
• update calculations of PCI Express performance calcule actualizare a PCI Express de performanta
• track errors to project possible weaknesses within the fabric. erori cale de a posibilelor puncte slabe in cadrul proiectului tesatura. This can suggest areas where greater potential exists for fatal errors in the future. Acest lucru poate sugera domenii in care exista un potential mai mare pentru erori fatale in viitor.

Uncorrectable Non-Fatal Errors Uncorrectable Erori non-fatale

Non-fatal errors mean that the integrity of the PCI Express fabric is not affected, but that information has been lost. Non-letale erori inseamna ca integritatea PCI Express tesatura nu este afectat, dar ca informatiile au fost pierdute. Non-fatal errors typically mean that a transaction has been corrupted, and the PCI Express hardware cannot correct the error. Non-letale erori de obicei, inseamna ca o tranzactie a fost corupt, iar hardware-ul PCI Express nu poate corecta eroarea. However, the PCI Express fabric continues to function correctly and other transactions are unaffected. Cu toate acestea, PCI Express tesatura continua sa functioneze corect si alte tranzactii nu sunt afectate. Recovery from a non-fatal error may or may not be possible. Recuperarea dintr-o eroare de non-letale poate sau nu poate fi posibil. The possibility of recovery rests in the hands of the device-specific software associated with the requester that initiated the transaction. Posibilitatea de recuperare revine in mainile-software specifice de dispozitiv asociat cu solicitantul care a initiat tranzactia.

Uncorrectable Fatal Errors Uncorrectable erori fatale

Fatal errors indicate that a link in the PCI Express fabric is no longer reliable. Data has been lost and every attempt to recover data under software control will likely fail also. erori fatale indica faptul ca un link din tesatura PCI Express nu mai este de incredere. Datele au fost pierdute si orice incercare de a recupera datele sub control software-ul va esua probabil, de asemenea. Such conditions affect all transactions that traverse a given link. Aceste conditii afecteaza toate tranzactiile care traverseaza un link dat. In some cases, the error condition leading to the fatal errors may be resolved by resetting the link. In unele cazuri, stare de eroare care sa conduca la erori fatale poate fi rezolvata prin resetarea link-ul. Alternatively, the specification invites implementation-specific approaches, in which software may attempt to limit the effects of the failure. Alternativ, caietul de sarcini invita abordari specifice de implementare, in care software-ul sa incerce sa limiteze efectele esec. The specification does not define any particular actions that should or could be taken by software. Caietul de sarcini nu defineste nici actiuni specifice pe care ar trebui sau ar putea fi luate de software.

[ Team LiB ] Echipa [Lib]

[ Team LiB ] Echipa [Lib]

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Rezumatul Eroare de logare si raportare

Actiunile intreprinse de catre o functie atunci cand o eroare este detectat este reglementata de tipul de eroare si setarile de eroare de configurare registrele aferente. Caietul de sarcini cuprinde diagrama din figura de la pagina 10 24 393, care specifica actiunile intreprinse de un dispozitiv la detectarea unei erori Aceasta diagrama presupune ca software-ul compatibil PCI Express este utilizat si nu acopera caz de manipulare de eroare atunci cand numai mostenirea software-ul PCI este folosit.

Figura 10 24. Schema de eroare de manipulare